1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a static random access memory (SRAM) device.
2. Description of the Related Art
Generally, in an SRAM device which is constructed by flip-flop type memory cells arranged in rows and columns, and a plurality of word lines and a plurality of bit line pairs connected to the memory cells, a precharging operation needs to be carried out before an access operation such as a write operation or a read operation is carried out.
In a first prior art SRAM device, one of the word lines is connected to each row of the memory cells, and one of the bit line pairs is connected to each column of the memory cells. This will be explained later in detail.
In the above-mentioned first prior art SRAM device, however, since the number of bit lines is the same as that of columns of the memory cells, the number of bit lines precharged by each precharging operation is large. As a result, the power dissipation is increased.
In a second prior art SRAM device, two word lines are connected to each row of the memory cells, and each column of the memory cells is interposed between two adjacent bit lines. In this case, the number of bit lines is the number of columns of the memory cells plus 1. As a result, the number of bit lines precharged by each precharging operation is reduced, thus reducing the power dissipation. This will also be explained later in detail.
In the second prior art SRAM device, since the number of bit lines cannot be smaller than that of columns of the memory cells, the reduction of the power dissipation is limited.